{"id":6495,"date":"2026-06-10T08:42:05","date_gmt":"2026-06-10T08:42:05","guid":{"rendered":"https:\/\/wiresawcutter.com\/?p=6495"},"modified":"2026-06-10T08:42:05","modified_gmt":"2026-06-10T08:42:05","slug":"semiconductor-fabrication-plant","status":"publish","type":"post","link":"https:\/\/wiresawcutter.com\/de\/blog\/semiconductor-fabrication-plant\/","title":{"rendered":"Halbleiterfabrik: Funktionsweise eines Wafer-Fab (Inside Tour)"},"content":{"rendered":"

A fabrication plant, called a fab, is the front-end manufacturing site where blank wafers are converted into patterned devices with deposition, lithography, etch, clean, metrology, and numerous repeat process loops.<\/p>\n

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Quick Specs<\/h2>\n\n\n\n\n\n\n\n
Common names<\/th>\nFab, semiconductor fab, wafer fab, foundry, front-end manufacturing plant<\/td>\n<\/tr>\n
Core function<\/th>\nBuild integrated circuits on a semiconductor wafer before back-end packaging and assembly. <\/td>\n<\/tr>\n
Capacity metric<\/th>\nWafer starts per month, or WSPM; OECD notes this metric is often normalized as 8-inch wafer equivalents. <\/td>\n<\/tr>\n
Cleanroom baseline<\/th>\nISO 14644-1 classifies cleanroom air by particle concentration, with particle sizes from 0.1 um to 5 um. <\/td>\n<\/tr>\n
2026 market context<\/th>\nSEMI forecasts semiconductor manufacturing equipment sales of $145B in 2026 and $156B in 2027. <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/section>\n

A fab is not a single machine room. It is a process chain, a cleanroom, a subfab, a utility plant, a data system, a safety system, and a supplier network rolled into a single tightly controlled manufacturing site. The same word can also describe different business models: an integrated device manufacturer makes its own chips, while a foundry makes wafers for other chip designers.<\/p>\n

That distinction is important for equipment buyers. A single wafer may journey through hundreds of process steps after delivery into the cleanroom, but several yield hits are already determined before that moment: crystal growth, ingot shaping, wafer slicing, lapping, polishing, cleaning, inspection. This article describes the fabrication plant itself first, then explains where wafer preparation and diamond wire slicing occur within the greater wafer flow.<\/p>\n

What Is a Semiconductor Fabrication Plant?<\/h2>\n

\"What<\/p>\n

A semiconductor fabrication plant is a front-end chip manufacturing facility that shapes electronic devices on silicon or compound-semiconductor wafers. Within the fab, process tools deposit, remove, pattern, measure, and clean thin films until the wafer contains many finished die ready for electrical test and back-end packaging.<\/p>\n\n\n\n\n\n\n\n\n
Term<\/th>\nMeaning<\/th>\nBuyer relevance<\/th>\n<\/tr>\n<\/thead>\n
Fab<\/td>\nA wafer-processing plant for front-end chip manufacturing.<\/td>\nDefines the environment that incoming wafers must survive.<\/td>\n<\/tr>\n
Foundry<\/td>\nA fab business that manufactures chips for outside design companies. <\/td>\nProcurement may specify customer-qualified wafer and process controls.<\/td>\n<\/tr>\n
IDM<\/td>\nA company that designs and manufactures its own chips.<\/td>\nWafer preparation may be tied to an internal process roadmap.<\/td>\n<\/tr>\n
OSAT<\/td>\nAn outsourced assembly and test provider used after front-end wafer processing.<\/td>\nPackaging needs can feed back into wafer thickness and saw-damage limits.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

For a process engineer, the fab boundary is not only a real estate boundary. It is a yield boundary. Film uniformity, defect density, particle control, wafer flatness, edge condition, and metrology repeatability all determine how much good die can leave the plant.<\/p>\n

The Fab Process Flow From Blank Wafer to Patterned Device<\/h2>\n

\"The<\/p>\n

The semiconductor fabrication process is an ordered loop. A wafer arrives as a prepared substrate, then moves repeatedly through film, pattern, remove, clean, and measure steps. Advanced chips can visit the same tool families multiple times.<\/p>\n

What is the semiconductor fabrication process?<\/h3>\n

This is the manufacturing process that forms integrated circuits on a wafer. The OECD labels this step as wafer fabrication, where deposition, etching, patterning, and associated steps form integrated circuitry before packaging.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Step<\/th>\nWhat Happens<\/th>\nControl Point<\/th>\n<\/tr>\n<\/thead>\n
Incoming wafer<\/td>\nPrepared silicon wafer or compound-semiconductor substrate enters the line.<\/td>\nFlatness, thickness, particles, edge chips, traceability.<\/td>\n<\/tr>\n
Clean<\/td>\nChemistry and DI water remove particles and films.<\/td>\nParticle counts, metal contamination, water purity.<\/td>\n<\/tr>\n
Deposition or oxidation<\/td>\nThin films are grown or deposited.<\/td>\nFilm thickness, uniformity, stress.<\/td>\n<\/tr>\n
Coat and expose<\/td>\nPhotoresist is applied, exposed through a mask, and developed.<\/td>\nOverlay, focus, dose, resist defects.<\/td>\n<\/tr>\n
Etch<\/td>\nSelected material is removed to transfer the pattern.<\/td>\nEtch rate, selectivity, sidewall profile.<\/td>\n<\/tr>\n
Ion implantation<\/td>\nDopants are added to set electrical behavior.<\/td>\nDose, energy, wafer temperature.<\/td>\n<\/tr>\n
CMP<\/td>\nChemical mechanical polishing flattens films between layers.<\/td>\nPlanarity, dishing, scratches, slurry residue.<\/td>\n<\/tr>\n
Metrology<\/td>\nMeasurements confirm film, pattern, and defect results.<\/td>\nTrend drift, tool matching, sampling plan.<\/td>\n<\/tr>\n
Test handoff<\/td>\nFinished wafers move toward probe, dicing, packaging, and assembly.<\/td>\nMap data, yield binning, wafer handling.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

This varies by device type. Logic, memory, analog, power devices, MEMS, and compound semiconductors differ by detailed recipe, but the manufacturing logic stays recognizable: keep the wafer clean, deposit film material, pattern it, etch away excess, measure the outcome, repeat.<\/p>\n

Cleanroom, Subfab, and Utility Levels: Why the Building Is Part of the Process<\/h2>\n

\"Cleanroom,<\/p>\n

A cleanroom is only the visible layer. Behind exist air handling, water, gases, chemicals, vacuum, exhaust, abatement, and power systems. A fab building successfully operates when these auxiliary systems act as consistently as the process tools.<\/p>\n

Why do semiconductor fabs need cleanrooms?<\/h3>\n

Particles, trace metals, organic residue, humidity swings, and electrostatic events can ruin small features on a wafer. ISO 14644-1<\/a> gives a shared air-cleanliness classification method based on particle concentration, which helps teams specify and verify cleanroom conditions. <\/p>\n

Some plant records still write clean room as two words, while newer fab teams often write cleanroom. The label matters less than the contamination control plan: air change rate, pressure cascade, gowning, carrier handling, material entry, and particle monitoring all need ownership. A clean room spec should map ISO 14644-1 targets to contamination control routines, or it stays a design target rather than a working fab discipline.<\/p>\n

For a U.S. fab expansion project, the NIST programmatic environmental assessment<\/a> is a useful baseline checklist because it treats air, water, utilities, hazardous materials, and waste as part of the semiconductor fab review, not as afterthoughts.<\/p>\n\n\n\n\n\n\n\n\n
Fab Layer<\/th>\nWhat It Supports<\/th>\nRisk if Weak<\/th>\n<\/tr>\n<\/thead>\n
Fan or interstitial level<\/td>\nFiltration, air movement, access to overhead services.<\/td>\nParticle spikes, pressure instability, hard maintenance access.<\/td>\n<\/tr>\n
Cleanroom level<\/td>\nLithography, deposition, etch, CMP, clean, metrology, FOUP movement.<\/td>\nWafer contamination, tool downtime, recipe drift.<\/td>\n<\/tr>\n
Clean subfab<\/td>\nPumps, gas cabinets, exhaust, point-of-use support, abatement.<\/td>\nSafety events, lost uptime, process variation.<\/td>\n<\/tr>\n
Utility level<\/td>\nPower, chilled water, DI water, wastewater, bulk gases, chemicals.<\/td>\nCapacity limits, permit delays, unplanned shutdowns.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n
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Engineering note: a fab quality problem can originate well beyond the lithography bay. Unstable water, poor exhaust control, old pump technology, or a contaminated transfer route can appear after the fact as yield losses, defect density issues, or unexplained metrology fluctuations.<\/p>\n<\/div>\n

Fab Scale Metrics: WSPM, Wafer Diameter, Tools, and Build Time<\/h2>\n

\"Fab<\/p>\n

Fab size gets easier to compare when the topic transitions from square footage to capacity. WSPM, wafer size, installed tool families, utility headroom, and ramp status become much more relevant than the physical size of the building shell.<\/p>\n\n\n\n\n\n\n\n\n\n
Metric<\/th>\nMeaning<\/th>\nQuestion to Ask<\/th>\n<\/tr>\n<\/thead>\n
WSPM<\/td>\nWafer starts per month; a capacity measure used for wafer fabs. <\/td>\nIs capacity quoted in native wafer size or 8-inch equivalents?<\/td>\n<\/tr>\n
Wafer diameter<\/td>\nCommon production lines include 200mm and 300mm wafers, with smaller sizes used in specialty lines.<\/td>\nDoes incoming wafer prep match the tool set?<\/td>\n<\/tr>\n
Process node<\/td>\nA technology class tied to device design and process capability.<\/td>\nIs the line mature, ramping, or in pilot work?<\/td>\n<\/tr>\n
Tool family mix<\/td>\nLithography, deposition, etch, clean, CMP, implant, metrology, and support tools.<\/td>\nWhich tool family limits throughput or yield?<\/td>\n<\/tr>\n
Ramp status<\/td>\nPlanned, under construction, qualification, pilot, or production.<\/td>\nAre suppliers preparing for samples or stable volume?<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

The OECD’s 2025 chip landscape database identifies 1,433 fabs with 1,326 in production, 53 under construction, and 54 planned. These distinctions are important, because the supplier timeline is different for a planned fab, a new R&D line, and a production wafer fab.<\/p>\n

The issue of WSPM also falls short. It fails to differentiate whether the fab is memory, logic, analog, power, MEMS, or a specialty material line. It lacks information on cycle time, product mix, queue time, or the location of process constraints within lithography, etch, metrology, cleaning, or facilities. For a wafer-prep supplier, WSPM serves as a initial indicator for estimating demand, not a full process outline. While a 300mm high-volume line, a 200mm specialty fab, and a compound-semiconductor pilot line each require pristine input wafers, their needs for slicing trials, wafer handling, proof of inspection, and support cadence will be distinct.<\/p>\n

Core Wafer Fab Equipment Families<\/h2>\n

\"Core<\/p>\n

The processing steps of wafer fab equipment fall into natural categories based on how they alter the wafer. SIA’s ecosystem framework segments equipment and material suppliers, as well as fabless, foundry, IDM and OSAT companies, offering valuable context for buyers mapping who impacts each step.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
Tool Family<\/th>\nProcess Function<\/th>\nMain Risk<\/th>\n<\/tr>\n<\/thead>\n
Lithography<\/td>\nTransfers circuit patterns through photoresist.<\/td>\nOverlay error, focus loss, defects, mask issues.<\/td>\n<\/tr>\n
Deposition<\/td>\nAdds films such as dielectrics, metals, and barrier layers.<\/td>\nFilm stress, thickness spread, particles.<\/td>\n<\/tr>\n
Etching<\/td>\nRemoves selected material after patterning.<\/td>\nProfile drift, residue, selectivity loss.<\/td>\n<\/tr>\n
Ion implantation<\/td>\nPlaces dopants into the wafer to change electrical properties.<\/td>\nDose error, channeling, thermal effects.<\/td>\n<\/tr>\n
CMP<\/td>\nFlattens films for the next patterning step.<\/td>\nScratches, dishing, erosion, slurry residue.<\/td>\n<\/tr>\n
Clean and wet process<\/td>\nRemoves residues, particles, and unwanted films.<\/td>\nMetal contamination, water marks, chemical carryover.<\/td>\n<\/tr>\n
Metrology and inspection<\/td>\nMeasures films, defects, patterns, and wafer state.<\/td>\nLate detection, false pass, poor sampling.<\/td>\n<\/tr>\n
Wafer preparation<\/td>\nCreates the input wafer before front-end processing.<\/td>\nKerf loss, TTV, warp, subsurface damage, particles.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

SEMI’s equipment forecast is a reminder that fab demand is not only about lithography headlines. Wafer fab equipment, test, assembly, packaging, power, chemicals, facilities, and materials all move together when new capacity comes online. <\/p>\n

Where Wafer Preparation and Diamond Wire Slicing Fit Before the Fab<\/h2>\n

\"Where<\/p>\n

Wafer fabrication starts after the substrate has already been made. Before a cleanroom sees the wafer, the material has moved through crystal growth, ingot shaping, slicing, edge work, lapping or grinding, polishing, cleaning, and inspection. A small slicing defect can become a large cost if it reaches a high-value process line.<\/p>\n

Diamond wire sawing is one common route for slicing hard and brittle materials because a fixed abrasive wire can reduce material loss and support thin-wafer work. Research on diamond wire sawing connects wire wear, cutting force, surface state, and wafer quality, which is why slicing parameters belong in fab-adjacent process planning. <\/p>\n

For silicon wafer projects, anchor RFQ discussions around process ranges such as 10-25 m\/s wire speed, 60-120 um wire diameter, 0.3-1.0 mm\/min feed rate, 20-40 N wire tension, TTV under 10 um, Ra 0.3-0.6 um, 100-180 um semiconductor wafer thickness, and 60-120 um kerf loss. The linked silicon wafer cutting wire saw<\/a> resource is the commercial handoff for those slicing requirements. <\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
Slicing Spec<\/th>\nMetric Check<\/th>\nRFQ Use<\/th>\n<\/tr>\n<\/thead>\n
Wire speed<\/td>\n10 m\/s equals 600 m\/min; 25 m\/s equals 1500 m\/min.<\/td>\nAsk whether the test cut used the same speed band.<\/td>\n<\/tr>\n
Wire diameter<\/td>\n60 um equals 0.06 mm; 120 um equals 0.12 mm.<\/td>\nTie wire size to kerf budget and breakage risk.<\/td>\n<\/tr>\n
Feed rate<\/td>\n0.3 mm\/min to 1.0 mm\/min is a narrow process band.<\/td>\nRecord feed rate with material lot and coolant.<\/td>\n<\/tr>\n
TTV target<\/td>\n10 um equals 0.01 mm.<\/td>\nCheck whether the measurement plan covers edge and center.<\/td>\n<\/tr>\n
Surface roughness<\/td>\nRa 0.3 um to 0.6 um equals 0.0003 mm to 0.0006 mm.<\/td>\nState whether post-cut polishing is part of the project.<\/td>\n<\/tr>\n
Wafer thickness<\/td>\n100 um to 180 um equals 0.10 mm to 0.18 mm.<\/td>\nReserve extra trial wafers for handling and fracture checks.<\/td>\n<\/tr>\n
Kerf loss<\/td>\n60 um to 120 um equals 0.06 mm to 0.12 mm.<\/td>\nUse it as a material-cost baseline for the quote.<\/td>\n<\/tr>\n
Trial window<\/td>\nA 2 months to 3 months pilot project can expose wire wear drift.<\/td>\nCompare the first batch with the 3 months baseline before scale-up.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n\n
Wafer-Prep Field<\/th>\nWhy a Fab Cares<\/th>\nSourcing Cue<\/th>\n<\/tr>\n<\/thead>\n
Thickness target<\/td>\nAffects handling, polishing allowance, and downstream mechanical risk.<\/td>\nState final and pre-polish thickness separately.<\/td>\n<\/tr>\n
TTV<\/td>\nPoor thickness uniformity can raise polishing load and flatness risk.<\/td>\nAsk for measured TTV under your cut recipe.<\/td>\n<\/tr>\n
Surface roughness<\/td>\nSets the burden for later lapping, polishing, and cleaning.<\/td>\nTie Ra target to the post-cut plan.<\/td>\n<\/tr>\n
Kerf loss<\/td>\nMaterial loss affects cost per wafer and yield per ingot.<\/td>\nMatch wire diameter and tension to material value.<\/td>\n<\/tr>\n
Wire wear<\/td>\nChanging cutting force can change wafer surface state.<\/td>\nDefine replacement rules and inspection intervals.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

The slicing method may vary for compound semiconductor projects. For power electronics and other hard and brittle substrate applications, compare the SiC wafer cutting saw<\/a> path with the silicon process. The sapphire cutting wire saw<\/a> page offers a comparable point of reference for LED and optical substrate work.<\/p>\n

Yield Risk: Contamination, Flatness, and Process Drift<\/h2>\n

\"Yield<\/p>\n

Rarely is wafer yield loss attributable to one cause. A fab team might identify a symptom in its probe data, but the problem might actually be residing in cleaning, handling, wafer geometry, film stress, tool drift or a supplier change made weeks ago.<\/p>\n\n\n\n\n\n\n\n\n\n
Risk Level<\/th>\nWhat to Watch<\/th>\nControl Method<\/th>\n<\/tr>\n<\/thead>\n
1. Incoming material<\/td>\nWafer thickness, bow, warp, edge chips, particles.<\/td>\nIncoming inspection and supplier certificates.<\/td>\n<\/tr>\n
2. Clean state<\/td>\nParticles, metals, organics, water marks.<\/td>\nClean recipes, particle monitors, carrier control.<\/td>\n<\/tr>\n
3. Tool drift<\/td>\nFilm thickness, etch rate, temperature, pressure, plasma behavior.<\/td>\nRun charts, chamber matching, preventive maintenance.<\/td>\n<\/tr>\n
4. Pattern transfer<\/td>\nOverlay, focus, dose, resist residue.<\/td>\nInline metrology and feedback loops.<\/td>\n<\/tr>\n
5. Late discovery<\/td>\nDefects found after expensive process time.<\/td>\nEarlier inspection and better sampling at high-risk steps.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

This is why wafer slicing isn’t a secondary issue. If a cut process results in hidden subsurface damage or unstable surface quality, the fab may not know there’s an issue until much later after some cost-adding processing steps in cleaning, polishing, deposition or thermal have already taken place.<\/p>\n

Process control starts before the first fab recipe. A supplier change in wire, coolant, feed rate, or handling can shift incoming wafer behavior enough to confuse later metrology trends.<\/p>\n

The 8-Variable Fab-to-Wafer Slicing Matrix<\/h2>\n

\"The<\/p>\n

The 8-Variable Fab-to-Wafer Slicing Matrix offers equipment buyers a concrete tool for mapping fab requirements to pre-fab slicing. It can be used prior to issuing an RFQ for a silicon wafer saw, multi-wire saw or lab slicing system.<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Variable<\/th>\nSpecify This<\/th>\nWhy It Matters<\/th>\n<\/tr>\n<\/thead>\n
1. Material<\/td>\nSilicon, SiC, sapphire, GaN, glass, ceramic, or test coupon.<\/td>\nHardness and brittleness change wire choice and feed behavior.<\/td>\n<\/tr>\n
2. Diameter or blank size<\/td>\nLab sample, custom ingot, 150mm, 200mm, 300mm, or non-round blank.<\/td>\nMachine envelope and wire path must fit the part.<\/td>\n<\/tr>\n
3. Thickness target<\/td>\nFinal thickness, pre-polish thickness, and tolerance.<\/td>\nThin wafers raise breakage and handling risk.<\/td>\n<\/tr>\n
4. Kerf budget<\/td>\nAllowed material loss per cut.<\/td>\nMaterial cost and wafer count per ingot depend on it.<\/td>\n<\/tr>\n
5. TTV limit<\/td>\nTotal thickness variation target, measured method, and sample plan.<\/td>\nTTV affects polishing allowance and flatness control.<\/td>\n<\/tr>\n
6. Surface finish<\/td>\nRa target, saw mark limit, and downstream finishing path.<\/td>\nRougher cuts can move cost into lapping and polishing.<\/td>\n<\/tr>\n
7. Throughput target<\/td>\nResearch, pilot, batch, or production line rate.<\/td>\nSingle-wire, endless loop, and multi-wire saw<\/a> systems serve different volume needs.<\/td>\n<\/tr>\n
8. Handling and inspection<\/td>\nCarrier, cleaning, wafer map, inspection, and traceability plan.<\/td>\nA good cut still fails if handling adds particles or chips.<\/td>\n<\/tr>\n
9. Change control<\/td>\nWire lot, coolant, tension, feed, and replacement rules.<\/td>\nStable inputs reduce unexplained process drift later.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

How to turn the matrix into a supplier brief<\/h3>\n

A useful RFQ does not start with “send a quote for a wire saw.” It starts with the wafer state the fab needs to receive. That means the buyer should share the material family, blank geometry, target thickness, cut face requirement, allowed kerf, inspection method, sample quantity, and follow-on process. A supplier can then talk about wire diameter, wire tension, feed rate, coolant, carrier design, throughput, and test cuts with fewer guesses.<\/p>\n