{"id":6523,"date":"2026-06-11T09:09:56","date_gmt":"2026-06-11T09:09:56","guid":{"rendered":"https:\/\/wiresawcutter.com\/?p=6523"},"modified":"2026-06-11T09:09:56","modified_gmt":"2026-06-11T09:09:56","slug":"wafer-thinning","status":"publish","type":"post","link":"https:\/\/wiresawcutter.com\/fr\/blog\/wafer-thinning\/","title":{"rendered":"Wafer Thinning Process: Back-Grind & Back-Lap Technology Explained"},"content":{"rendered":"
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Wafer thinning is the back-end step where a finished silicon wafer is ground and polished down from its full handling thickness to a fraction of it. It rarely makes headlines, yet every stacked memory cube, every thin power device, and every smartcard chip depend on it. This guide walks through what wafer thinning is, the methods that do it, the thickness targets that matter, and the quality limits that decide whether a thinned wafer survives to become working die.<\/p>\n

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Quick Specs: Wafer Thinning at a Glance<\/h3>\n\n\n\n\n\n\n\n
Starting thickness (200\/300 mm)<\/td>\n~725\u2013775 \u00b5m<\/td>\n<\/tr>\n
Common thinned target<\/td>\n75\u201350 \u00b5m; ultrathin <50 \u00b5m for 3D\/HBM<\/td>\n<\/tr>\n
Core methods<\/td>\nCoarse + fine grinding \u2192 CMP \/ plasma or wet etch (stress relief)<\/td>\n<\/tr>\n
Key quality metrics<\/td>\nTTV, subsurface damage depth, die break strength, edge integrity<\/td>\n<\/tr>\n
Where it sits<\/td>\nAfter slicing, before dicing (die singulation)<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n

What Is Wafer Thinning?<\/h2>\n

\"What<\/p>\n

Wafer thinning is the process of reducing a finished semiconductor wafer’s thickness after device fabrication, typically from about 775 \u00b5m down to 75\u201350 \u00b5m and below, using back-side grinding, polishing, and etching.<\/strong> It happens after the wafer is sliced from the ingot and before it’s diced into individual chips, so the front-side circuits are protected while the back side is removed. Removing that bulk give a thinner, lower-profile die that stacks better and conducts heat faster.<\/p>\n

Wafers start thick on purpose. At 200 mm or 300 mm, a wafer is roughly 725\u2013775 \u00b5m thick to stay flat and survive the heat cycles of front-end processing, according to the Wikipedia overview of wafer backgrinding<\/a>. Once the circuits are built, all that supporting silicon become dead weight that blocks stacking and slows heat removal, so it’s ground away. You’ll also see the step called backgrinding (or back grinding), backlap, backfinish, or backside grinding; they refer to the same family of operations.<\/p>\n

Grinding a production wafer too far is risky: it cracks, because the thinned back side carries grinding stress the thick front side never had to absorb. In practice, fabs treat the final 50 \u00b5m of silicon as the most fragile material on the whole line.<\/p>\n

It helps to place thinning in the back-end flow: a diamond wire saw slices the wafer<\/a> from the ingot, the front side is patterned in the fab, then the wafer is thinned<\/em> from the back, and finally it’s diced into chips. For the full upstream picture, see our guide to the semiconductor manufacturing process<\/a>.<\/p>\n

Why Wafers Are Thinned<\/h2>\n

\"Why<\/p>\n

Wafers are thinned to shrink package height, enable 3D stacking, cut thermal resistance, and lower electrical losses.<\/strong> A shift from flat system-on-chip designs to 3D-ICs and advanced packages is the main driver: thinner die let signals travel shorter distances with less energy, as the Semiconductor Engineering feature on thin wafer processing<\/a> explains.<\/p>\n

A few concrete pull on the thinning rope:<\/p>\n